Source Couple Logic (SCL): Theory and Physical Design
- 1 VLSI Design Center, Malaysia
Abstract
This study describes and presents the analysis for the Source-Coupled Logic (SCL) inverter as will as the effect of submicron layout parasitics. The SCL inverter circuit model and its operation is defined. The analysis for the SCL is carried from the point of view of input/output voltage characteristics and the effect of noise margin. The inverter gate delay model is described and the effect of biasing current on the delay is shown. The result shows that, the delay of the SCL inverter is decreased as biasing current increase. The simulation is done based on the 0.18 µ Silterra PDK. Different layouts for SCL inverter have been investigated for its effect on output voltage swing, switching noise and the area. The results show an important effect on the SCL output signals. Post-Simulation was carried out on all proposed layouts using HSPICE and using 0.35 µ MIMOS Berhad PDK. The layout was done using Virtuous from Cadence where as the extraction done using Mentor Graphic-Caliber Interactive tool.
DOI: https://doi.org/10.3844/ajeassp.2008.24.32
Copyright: © 2008 Mohamed Azaga and Masuri Othman. This is an open access article distributed under the terms of the
Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.
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Keywords
- Source Couple Logic (SCL)
- CMOS layout
- RC parasitic in layout
- analog circuit layout